1. Field of the Invention
The present invention relates generally to a semiconductor device and a fabrication process thereof. More specifically the invention relates to a MOS transistor, in which connection between a diffusion layer and a wiring is established through a monocrystalline silicon layer provided in direct connection with the surface of a wiring layer.
2. Description of the Related Art
The increase in the package density of semiconductor device because of the decreasing size of semiconductor elements, the storage capacity of DRAMs is four times greater than the storage capacity of three years ago, for example. To obtain an increase in package density in the semiconductor device, it is essential to realize downsizing of not only the semiconductor elements per se but also wiring establishing mutual connections between the semiconductor elements as well as contact hole connecting the wiring and the semiconductor element. In view of demand for forming the semiconductor elements and contact hole at minimum dimensions defined in a current design rule at each timing, there have been proposed various structure for contact holes called as self-aligning type contact holes.
The inventors have presented new proposal for self-aligning type contact hole in paper of IEDM-95, pp 665 to 668 (Speech Number 27.4.1) in International Electron Devices Meeting, held in December 1995. The proposal is to form a monocrystalline silicon layer on an exposed surface of a diffusion layer provided on the surface of the silicon substrate which has major plane of {100} face, in self-aligned manner by way of anisotropic (not isotropic) selective epitaxial growth.
For example, anisotropic selective epitaxial growth of the monocrystalline silicon layer on an N-type diffusion layer is performed by means of ultra-high vacuum chemical vapor deposition: UHV-CVD) device in an order of 10.sup.-7 Pa, with employing disilane (Si.sub.2 H.sub.6) and hydrogen phosphide (PH.sub.3) as a primary material gas and doping gas at a temperature about 700.degree. C. At this time, monocrystalline silicon layer primarily grown in &lt;100&gt; direction perpendicular to the major surface of the silicon substrate (in comparison with &lt;110&gt; direction).
After the foregoing report, the inventors have made study for an appropriate condition of anisotropic selective epitaxial growth on the basis of the foregoing report, and also has attempted to experimentally fabricate DRAM according to 0.25 .mu.m design rule (minimum processing dimension; F=0.25 .mu.m (250 nm)).
Further discussion will be given with reference to FIGS. 12 and 13 which are diagrammatic plan view and diagrammatic sectional view of DRAM. The shown DRAM fabricated by anisotropic selective epitaxial growth has COB structure, in which a bit line is located below a capacitor as will be discussed below. At this time, a mask alignment margin (=.alpha.) in a photolithographic process is approximately 50 nm.
Here, FIGS. 12A and 12B are a diagrammatic plane view of the multi-level semiconductor device, in which FIG. 12A shows a positional relationship between a gate electrode which also serves as an active region and a word line and a monocrystalline silicon layer, and FIG. 12B shows a positional relationship between a gate electrode and monocrystalline silicon layer, bit lines and storage node electrodes. Also, FIGS. 13A, 13B and 13C are diagrammatic sections taken along lines A--A, B--B and C--C of FIG. 12. It should be noted that, in FIGS. 12A and 12B, gate electrode and bit line are illustrated thinner than actual width for facilitating understanding of the positional relationship.
The major surface of P-type silicon substrate 301 is {100} face. A specific resistance of the P-type silicon substrate is about 5.OMEGA..multidot.cm. An orientation flat of the silicon wafer forming the P-type silicon substrate 301 is an edge of &lt;110&gt; direction. An active region 302 on the surface of the P-type silicon substrate is surrounded by an isolation region which constituted of an LOCOS type field oxide layer 305 with a thickness of about 300 nm and a P.sup.- type diffusion layer 304 (for serving as channel stopper and punch through stopper) provided on the bottom surface of the field oxide layer 305.
The active regions 302 is regularly arranged on the major plane of the P-type silicon substrate 301. Peripheral edge of the active region consists of a edge of &lt;110&gt; direction. In other words, the active region 302 is defined by the edge of &lt;110&gt; direction. The minimum width (channel width) and minimum interval of the active region 302 are both F (approximately 0.25 .mu.m (250 nm)).
The gate electrodes 311 with a layer thickness of approximately 150 nm, which also serves as word lines, extend across the surface of an active region 302 via a gate oxide film 306 of thickness of approximately 8.5 nm provided on the surface of the active region 302 by thermal oxidation. At least in a region immediately above the active region 302, these gate electrodes 311 extend in perpendicular to the active region. The width (gate length), interval and wiring pitch of the gate electrodes 311 are respectively about F, F and 2F (=0.5 .mu.m (500 nm)).
The gate electrode 311 is formed by stacking a tungsten silicide layer in a thickness of about 100 nm over an N.sup.+ type polycrystalline silicon layer in a thickness of about 50 nm. The N.sup.+ type polycrystalline silicon layer is formed through CVD method at a temperature about 700.degree. C. using dichlorsilane (SiH.sub.2 Cl.sub.2) as a material gas and hydrogen phosphide as doping gas. On the other hand, the tungsten silicide layer is formed by sputtering.
The upper surface of the gate electrode 311 is directly covered with a oxide silicon layer cap 312 with a thickness of about 70 nm. On the surface of the active region 302, N.sup.- type diffusion layers 313a and 313b respective having about 100 nm of junction depth, in self-alignment with the gate electrodes 311 and the field oxide layer 305. These N.sup.- type diffusion layers 313a and 313b are formed by ion implantation of about 2.times.10.sup.13 cm.sup.-3 of phosphorous or arsenic at 30 keV.
The side surfaces of the gate electrode 311 and the oxide silicon layer cap 312 are directly covered with an oxide silicon layer spacer 314 in a thickness of about 50 nm (=d (=.alpha.)). The gate oxide layer 306 provided on the surface of the active region 302 is removed in self-align manner with respect to the field oxide layer 305 and the silicon oxide layer space 314 thereof to expose the surfaces of the N.sup.- type diffusion layers 313a and 313b in these regions.
A width of the exposed surface in an alignment. direction of two gate electrodes 311 is about 150 nm (=F-2d). The width of the exposed surface in the portion disposed between the field oxide layers 305 is about 250 nm (=F). The silicon oxide layer forming the silicon oxide layer cap 312 is consisted of the silicon oxide layer formed in a thickness of about 100 nm by CVD methods initially. However, the layer thickness will becomes thinner in the step forming the silicon oxide layer spacer 314.
The height (about 230 nm from the major surface of the P-type silicon substrate 301) of the upper surface of the silicon oxide layer cap 312 at the position immediately above the active region 302 is lower than the height (about 370 nm from the major surface of the P-type silicon substrate) of the upper surface of the silicon oxide cap 312, in the extent of 140 nm.
The exposed surface of the N.sup.- type diffusion layers 313a and 313b are directly covered with monocrystalline silicon layers 316a and 316b with a thickness of about 500 nm containing impurity in the content of about 1.times.10.sup.19 cm.sup.-3. In the exposed surface of the N.sup.- type diffusion layers 313a and 313b, N.sup.+ type diffusion layers 315a and 315b having a (junction) depth in the extent of 70 nm, are provided. These N.sup.+ type diffusion layers 315a and 315b are formed by solid phase diffusion of phosphorous from respective of the monocrystalline silicon layers 316a and 316b.
Source and drain region 318a is constituted of the N.sup.- type diffusion layer 313a, N.sup.+ type diffusion layer 315a and the monocrystalline silicon layer 316a, and source and drain region 318b is constituted of the N.sup.- type diffusion layer 313b, N.sup.+ type diffusion layer 315b and the monocrystalline silicon layer 316b. These monocrystalline silicon layers 316a and 316b serve as contact pads for a node contact hole and a bit contact hole discussed later.
The major upper surfaces of these monocrystalline silicon layers 316a and 316b are constituted with {100} face perpendicular to the major surface of the P-type silicon substrate 301. The side surfaces of these monocrystalline silicon layers 316a and 316b are constituted of {110} face perpendicular to the major surface of the P-type silicon substrate 301. The monocrystalline silicon layers 316a and 316b are slightly extended over a portion in the vicinity of bird's beak and a portion in the vicinity of the upper end of the silicon oxide layer spacer 314.
The upper surface and the side surface of the monocrystalline silicon layers 316a and 316b do not directly intersect, in strict sense, but intersect via a facet (which is constituted by stacking terrace of silicon monoatomic layer forming {100} face parallel to the major surface of the P-type silicon substrate 301). It should be noted that, in the following discussion, discussion will be given assuming that the facet is included in a part of the upper surface unless otherwise mentioned specifically.
These monocrystalline silicon layers 316a and 316b are formed by employing the UHV-CVD device at a temperature of 625.degree. C., under a pressure of about 1.times.10.sup.-2 Pa, with disilane in a flow rate of 2.0 sccm and a doping gas (hydrogen phosphide diluted into 1% by hydrogen (H.sub.2)) in a flow rate of 0.2 sceem.
At this time, a growth speed of {100} face of the monocrystalline silicon layers 316a and 316b parallel to (and perpendicular to) the major surface of the P-type silicon substrate 301 in &lt;100&gt; direction is about 10 nm/min. When the base layer is silicon oxide layer, the growth speed of {110} face of the monocrystalline silicon layers 316a and 316b in &lt;110&gt; direction is about one twentieth of the growth speed of {100} face in &lt;100&gt; direction.
A width extended over a portion in the vicinty of the upper end of the oxide silicon layer spacer 314 is about 10 nm to 25 mm (narrower than the mask alignment margin (.alpha.=50 nm).
Here, the peripheral edges of the active region 302 consists of the edges of &lt;110&gt; direction, and the gate electrode 311 extends across the active region 302 in &lt;110&gt; direction. Therefore, the monocrystalline silicon layers 316a and 316b grow mainly in &lt;100&gt; direction perpendicular to the major surface of the P-type silicon substrate 302. When &lt;100&gt; direction is included in the direction of the gate electrode 311 in the edge forming aethe peripheral edge of the active region 302 or the portion extending across the active region 302, the side surface of the monocrystalline silicon layer constituted of {100} face parallel to this direction also selectively grows in the direction perpendicular to this direction, and it is not desirable.
The P-type silicon substrate 301 including an N-channel MOS transistor is covered with a first interlayer insulation layer 321. The first interlayer insulation layer 321 is a silicon oxide type insulation layer, such as a stacked layer of silicon oxide layer and BPSG layer by CVD method, for example, and has a flattened upper surface by chemical mechanical polishing (CMP) or so forth. The layer thickness of the first interlayer insulation layer above the monocrystalline silicon layer 316a or so forth is about 300 nm, for example. In the first interlayer insulation layer 321, a bit contact hole 322 having a diameter of about F and reaching the monocrystalline silicon layer 316b through the interlayer insulation layer 321, is formed. The bit contact layer 322 is filled with a contact plug 323 of N.sup.+ type polycrystalline silicon layer, for example.
The bit lines 324 provided on the upper surface of the first interlayer insulation layer 321 a re directly connected to the contact plug 323 and thus connected to source and drain region 318b. These bit lines 324 is formed by a tungsten suicide layer in a thickness of about 120 nm, for example. The minimum width and minimum interval of the bit lines 324 are both approximately F. The width of the bit line 324 at a portion of the bit contact hole 322 is about 0.35 .mu.m (=F+2.alpha.) , and the wiring pitch of the bit lines 324 is about 0.6 .mu.m (=2F+2.alpha.).
The first interlayer insulation layer 321 together with the bit lines 324 are covered with a second interlayer insulation layer 331. The second interlayer insulation layer 331 is also formed with silicon oxide type insulation layer. The thickness of the second interlayer insulation layer at the portion on the upper surface of the bit line 324 is about 300 nm. The upper surface of the second interlayer insulation layer 331 is also planarized.
Node contact holes 332 having diameters of approximately F and extending through the first and second interlayer insulation layers 321 and 331 reach the monocrystalline silicon layer 316a. The node contact holes 332 are filled with contact plugs 333 consisted of N.sup.+ type polycrystalline silicon layers, for example. Storage node electrodes 334 provided on the upper surface of the second interlayer insulation layer 331 is consisted of N.sup.+ type polycrystalline silicon layers having a layer thickness of about 800 nm. The storage node electrodes 334 are directly connected to the contact plugs 333 and thus connected to a source and drain region 318a.
The interval and minimum width of each of these storage electrodes 334 are about F and F+2.alpha., respectively. The upper surface and the side surface of the storage node electrode 334 and at least a part of the second interlayer insulation layer 331 are directly covered with a capacitive insulation layer 335 consisted of a stacked film (so called ONO film), in which silicon oxide layer, silicon nitride layer and silicon oxide layer are stacked in sequential order. The layer thickness of the capacitive insulation layer 335 as converted into the layer thickness of the silicon oxide layer is about 5 nm.
The surface of the capacitive insulation layer 335 is directly covered with a cell plate electrode 336 of N.sup.+ type polycrystalline silicon layer having a thickness of about 150 nm, for example. The surface of the cell plate electrode 336 is directly covered with a surface protective layer 341 consisted of the silicon oxide type insulation layer. The layer thickness of the surface protective layer 341 immediately above the storage node electrode 334 is about 300 nm.
If the monocrystalline silicon layers 316a and 316b of the foregoing DRAM are formed by known isotropic selective epitaxial growth method, since the interval between the N.sup.- type diffusion layer 313a is about 350 nm, an interval of the monocrystalline silicon layer serving as the contact pad for the node contact hole becomes too narrow to certainly obtain necessary height to serve as the contact pad. It is preferred that the height of the contact pad is higher than at least the upper surface of the silicon oxide layer cap 312.
In contrast to this, the monocrystalline silicon layer formed by anisotropic selective epitaxial growth set forth above has higher growth speed of the {100} face in &lt;100&gt; direction in comparison with the growth speed of {110} face in &lt;110&gt; direction. Therefore, as shown in FIGS. 12a and 12B and other figure, it is facilitated to provide necessary interval between the monocrystalline silicon layer 316a and the monocrystalline silicon layer 316b and between two adjacent monocrystalline silicon layers 316a so as to avoid possibility of occurrence of shorting.
However, associated with that nature of the anisotropic selective epitaxial growth that growth speed of the {100} face in &lt;100&gt; direction is higher than the growth speed of {110} face in &lt;110&gt; direction, a new problem is encountered. Such problem will be discussed with reference to the diagrammatic illustration in FIG. 14.
In the anisotropic epitaxial growth, the growth speed of the {110} face in &lt;110&gt; direction is about one twentieth of the growth speed of the {100} face in &lt;100&gt; direction. Therefore, after the upper surfaces of the monocrystalline silicon layers 316a and 316b reach in the vicinity of the upper end portion of the silicon oxide layer spacer 314, growth of the {110} faces of the monocrystalline silicon layers 316a and 316b in &lt;110&gt; direction is initiated.
As a result, an overlapping width of the monocrystalline silicon layers 316a and 316b over the a portion in the vicinity of the upper end portion of the silicon oxide layer spacer 314 (further over the upper surface of the silicon oxide layer cap 312) becomes narrower than the overlapping width of the monocrystalline silicon layers 316a and 316b over the upper surface of the field oxide layer 305.
In such condition, when the node contact hole 322 is to be formed, unless an offset .delta. (which should be 0.ltoreq..delta..ltoreq..alpha.) of mask alignment is zero, the upper end portion of the silicon oxide layer 314 and part of the silicon oxide layer cap 312 can be removed by etching to form locally thin portions of the silicon oxide layer cap 312 and the silicon oxide layer spacer 314 covering the gate electrode 311, and furthermore, a part of the gate electrode 311 is exposed to the bottom of the node contact hole 322.
In order to enable the monocrystalline silicon layer 316a and so forth to satisfactorily serve as the contact pads, it is essential that only upper surface of the monocrystalline silicon layers 316a or so forth are exposed to the bottom of the node contact hole 322 or so forth. Accordingly, in this case, the monocrystalline silicon layer 316a or so forth becomes insufficient to serve as the contact pads. For this reason, leak current between the source and drain region (storage node electrode of the capacitor in this case) and the gate electrode can be increased and further can cause shorting therebetween.
It should be noted that, in this case, it becomes as possible to certainly provide sufficient overlapping width of the monocrystalline silicon layer corresponding to a mask alignment margin (.alpha.) on the silicon oxide layer cap 312 by providing the monocrystalline silicon layer of the layer thickness of about 2 .mu.m by anisotropic selective epitaxial growth, for example. However, the monocrystalline silicon layer having such height is not practical and should cause problems in workability and so forth in the prior art process.